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Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 2). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
Figure 2. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 3 ).
Figure 3. Start and Stop Definition
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 3 ).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. . The EEPROM sends a “0” to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode
that is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the com-
pletion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles
2. Look for SDA high in each cycle while SCL is high
3 . Create a start condition as SDA is high.
6
AT24C02A/04A
0976Q–SEEPR–8/05
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